1. Field of the Invention
The invention relates to the general field of field emission devices, more particularly to the formation of the microtip cavity.
2. Description of the Prior Art
Cold cathode electron emission devices are based on the phenomenon of high field emission wherein electrons can be emitted into a vacuum from a room temperature source if the local electric field at the surface in question is high enough. The creation of such high local electric fields does not necessarily require the application of very high voltage, provided the emitting surface has a sufficiently small radius of curvature.
The advent of semiconductor integrated circuit technology made possible the development and mass production of arrays of cold cathode emitters of this type. In most cases, cold cathode field emission displays comprise an array of very small conical emitters, each of which is connected to a source of negative voltage via a cathode conductor line or column. Another set of conductive lines (called gate lines) is located a short distance above the cathode lines at an angle (usually 90.degree.) to them, intersecting with them at the locations of the conical emitters or microtips, and connected to a source of positive voltage. Both the cathode and the gate line that relate to a particular microtip must be activated before there will be sufficient voltage to cause cold cathode emission.
In FIG. 6 we show, in schematic cross-section, the basic elements of a single field emission device (FED). A portion of a cathode column is shown as layer 2 on the surface of insulating substrate 1. Located on layer 2 is microtip 51, typically a cone of height about one micron and base diameter about one micron and comprising molybdenum or silicon, though other materials may also be used. In many embodiments of the prior art, local ballast resistors (not shown here) may be in place between the cone and the cathode column.
A hole in layer 4, directly over the microtip 51 allows streams of electrons to emerge from the tips when sufficient voltage is applied. Because of the local high fields right at the surface of the microtips, relatively modest voltages, of the order of 100 volts are sufficient. It will be noted that a cavity (designated 61) has been formed in dielectric layer 3 in order to house microtip 51. In the present invention we will be concerned with improved methods for forming such a cavity.
In the prior art, it is standard practice to form the microtip housing cavity in two separate steps. First, a hole is etched in the gate layer (layer 4 in FIG. 6) then, using a different etchant, layer 4 serves as a mask while layer 3 (also in FIG. 6) is etched. The second etchant is chosen so as not to attack layer 4 so etching can be allowed to proceed for long enough to expose enough of layer 2 to form a base for microtip 51 and to cause significant undercutting of layer 4.
A good description of this prior art method of forming the cavity is given in Huang et al. (U.S. Pat. No. 5,461,009 October 1995). Their equivalent of layer 3 in FIG. 6 is composed of silicon or aluminum oxide while their equivalent of our layer 4 is composed of silicon nitride.
The invention of Doan et al. (U.S. Pat. No. 5,372,973 December 1994) is primarily concerned with how to minimize the gate to tip spacing. To this end, the microtip is formed first and then the cavity is formed around it. This makes for a self-aligning process. Depending on the choice of materials, the cavity may be significantly larger than the microtip or be confined to a small volume near the surface of the microtip.
Nakamoto et al. (U.S. Pat. No. 5,499,938 March 1996) are mostly concerned with novel methods for forming the microtips. Like Doan et al., they form the microtip first and then build the cavity around it.